4.6 Limitations in the Simics MAI Implementation
- Simics does not currently have an address calculation phase
which means that the address for a store instruction is calculated when
all input registers are known, not as soon as the registers used in
the address calculation are known. This may cause a store to prevent other
operations from running as soon as they could have, and thus limit the
parallelism achievable by the model more than what is theoretically
- (SPARC only): Block loads block operation and stores obey
register dependences, but the hardware does not. As long as the running code is
written so that it does not rely on pipeline effects, this limitation should
not be a problem.
- The instructions tree is not saved in a checkpoint. Only the
committed architectural state and retired stores are saved.
- Some x86 transactions are non-stallable and will bypass the LSQ. This
includes stack transactions performed when taking an interrupt or an exception,
hardware tablewalks, saving the entire fp state or doing a 10-byte fp