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2   Introduction

This document describes how to model cycle accurate microprocessors and memory systems with Simics. A basic knowledge of Simics and its time modeling (refer to Understanding Simics Timing in Simics User Guide) is recommended before reading on.


Simics is a system-level instruction set simulator; its default CPU models are functionally very close to their real counterparts, detailed enough to boot and run unmodified operating systems and applications. At this level of abstraction, exact timing is rarely a requirement. Simics considers the execution of an entire instruction, an exception or an interrupt as an atomic operation in the simulation process: it takes exactly one cycle.

Simics allows a user module to take control over the memory system timing, deciding how many cycles each memory transaction requires to complete. Although this model can be sufficient to simulate the effects of caches, it still enforces Simics's concept of atomic, in-order execution.


Simics Micro Architectural Interface (MAI) was designed to overcome these limitations while keeping the power of a functional full-system simulator. Using MAI, Simics can model the timing behavior of modern processors with deep pipelines and still run unmodified system-level software.

The basic idea behind MAI is to let the user decide when things happen, while Simics handles how things happen. A user module chooses when to fetch, decode, execute and commit instructions, using MAI to tell Simics to actually perform the actions. Execution is supervised by Simics; it will notify the user when program order consistency is violated, but even these warnings may be overridden.

Simics MAI supports out-of-order execution, multi-processor and multi-threading, branch and value speculation; for each processor, it gives the user control over an execution tree that represents the possible execution paths. The user module builds these paths by speculating on output values and branches.


Simics MAI is available for the SPARC-V9 and x86 architectures. The SPARC-V9 architecture, introduced in Simics 1.4, is more mature than the x86 implementation delivered with Simics 2.0, but both support all MAI features.

Note: The Parameterized execution mode that was present up to Simics 1.8 (for SPARC only) is not available any more. The ooo-micro-arch module mimics its behavior and should be used instead.

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