The Micro-Architectural Interface allows the user module to specify all actions a processor should take during one clock cycle. This gives the user total control of the scheduling and latencies of the different instruction phases described earlier. The module is of course not limited to these phases alone, it has full freedom to add its own phases or pipeline stages. The simulation is driven forward by calling API functions that will pass instructions through the different phases. It is up to the user module to decide when things should happen while Simics will still perform what should happen. This allows the user to concentrate on the timing aspects of the processor while leaving the functional details to Simics.
This extensive API allows the user to control when instruction should be fetched, decoded, executed, etc. As described earlier, the active instruction state is stored in a tree. This helps the user keep track of dependences between instruction and prevents instructions from being executed before input data is available.
Complete details of all API functions are documented in appendix A.
4.1 Cycle Handler
4.2 Creating the Instruction Tree
4.3 Proceeding Instructions
4.4 Discarding Instructions
4.5 Synchronous Instructions
4.6 Limitations in the Simics MAI Implementation