DMA controller implementing bus-master-ide.
Non-zero if the DMA controller is ready for transfer.
Time in seconds between state changes.
Interrupt request status.
Interrupt target implementing the simple-interrupt interface.
Currently selected addressing mode (bit 6 in the drive/head register).
Master device. Must implement the ide-device interface.
If set, the controller will accurately model DMA transfer bandwidth (infinite bandwidth otherwise).
Set to one if this is a primary IDE controller.
Currently selected drive (bit 4 in the drive/head register).
Slave device. Must implement the ide-device interface.
|info||print information about the device|
|status||print status of the device|