The Alpha EV5 CPU which is the recipient of all interrupts, and must export the alpha-ev5 interface.
(mask-1, mask-2, mask-3) are the interrupt mask registers writable at port 0x804, 0x805, and 0x806. Each interrupt can be individually masked by setting the appropriate bit in a mask register. An interrupt is disabled by writing a 1 to the desired position in the mask register.
(request-1, request-2, request-3) are the interrupt request registers readable from port 0x804, 0x805, and 0x806. In these registers, a 1 means that the interrupt source has asserted its interrupt.