(phys-bits, virt-bits) Number of bits in physical and virtual addresses.
((address profiler, view)*) Address profiler views selected for this processor. Affects only the display of profiling information, and has nothing to do with collecting it.
This attribute should contain a list of lists: one list for each address profiler view you want to select (in the order they are to appear), each containing first the address profiler object, then the index of the desired view.
Implemented architecture (mips32)
COP0 Register 7. BadVAddr register
This attribute is TRUE if the processor uses big-endian byte order and FALSE if it uses little-endian.
True if this processor supports branch profiling in -stall mode, false otherwise.
COP0 Register 13. Cause register
COP0 Register 11. Compare register
COP0 Register 16. Configuration register, sel 0
COP0 Register 16. Configuration register, sel 1
COP0 Register 16. Configuration register, sel 2
COP0 Register 16. Configuration register, sel 3
COP0 Register 4. Context register
COP0 Register 9. Count register
The group that this processor belongs to. A cpu group is a collection if cpus that may share memory and/or send interrupts between them. The group must implement the "cpu_group"interface.
Current context object.
Modeling parameter related to processor scheduling.
Time measured in cycles from machine start.
COP0 Register 28. DataLo register, sel 1
Force compile of block.
COP0 Register 23. Debug register
Indicates if current instruction is in a branch delay slot
COP0 Register 24. Depc register
COP0 Register 31. Desave register
Target register allocation enable.
Obsolete attribute that was used to keep information about the current memory transaction if is_stalling is set.
TRUE if the processor is enabled. If FALSE, it will see time (cycles) pass but not execute steps.
COP0 Register 10. EntryHi register
COP0 Register 2. EntryLo0 register
COP0 Register 3. EntryLo1 register
COP0 Register 14. Epc register
COP0 Register 30. ErrorEpc register
((object, description, time)*). All events in queue with a human-readable description. The attribute is indexed by queue (Sim_Queue_Step/Time).
Processor clock frequency in MHz.
General purpose registers
COP0 Register 0. Index register
Instruction fetch line size for this processor.
Instruction fetch mode
TRUE if the processor is currently stalling by request of a timing-model.
Joint TLB, [[virtual_base, page_size_log2, asid, g, [physical_base, c, d, v], [physical_base, c, d, v]]*].
COP0 Register 17. LLaddr register
LLbit (ongoing LL/SC)
Lock granularity of atomic instructions
When non-zero, the internal load/store queue is enabled. Only applicable if ooo-mode is "micro-architecture"
(internal) Set debug file for MAI
Base 2 logarithm of memory profiling granularity.
The minimum size (in bytes) of a cache line that can be represented by Simics (when connecting a cache memhier).
((name, user-value, supervisor-value), ...) List of per-mode counters.
Next Program Counter
"in-order" or "micro-architecture".
COP0 Register 5. PageMask register
Physical memory space. Must implement both the memory-space and the breakpoint interface.
COP0 Register 15. PrID register
Simics internal processor number for this CPU. Each processor must have a unique processor number. This attribute can only be set as part of an initial configuration.
COP0 Register 1. Random register
Highest index used for the 'Random' register. Default is the last jtlb entry.
The number of cycles the processor will stall
If is_stalling is set, this contains information about the current memory operation.
COP0 Register 12. Status register
"constant" indicates a constant finite step/cycle factor; "infinite" means that steps are run without advancing time.
((object, value, slot, step)*). Pending step queue events. object must implement the event_poster interface.
(q, p, r) where q/p is the step per cycle rate, p is a power of 2 and r indicates how much of a cycle that the current step has consumed.
Number steps executed since machine start.
COP0 Register 28. TagLo register, sel 0
((object, value, slot, cycle)*). Pending time queue events. object must implement the event_poster interface.
Force allocation of memory.
Turbo engine debug level.
Allocate all code space in the current block.
Start of heap.
Max number of blocks.
Max translation unit size.
When set to one, print stats.
Direct stack pointer enable.
Direct DSTC lookup enable.
Off page chaining enable.
Nonzero if the wait instruction is running
COP0 Register 18. WatchHi register
COP0 Register 18. WatchLo register
COP0 Register 6. Wired register