(phys-bits, virt-bits) Number of bits in physical and virtual addresses.
((address profiler, view)*) Address profiler views selected for this processor. Affects only the display of profiling information, and has nothing to do with collecting it.
This attribute should contain a list of lists: one list for each address profiler view you want to select (in the order they are to appear), each containing first the address profiler object, then the index of the desired view.
Implemented architecture (alpha)
This attribute is TRUE if the processor uses big-endian byte order and FALSE if it uses little-endian.
True if this processor supports branch profiling in -stall mode, false otherwise.
The group that this processor belongs to. A cpu group is a collection if cpus that may share memory and/or send interrupts between them. The group must implement the "cpu_group"interface.
Current context object.
Modeling parameter related to processor scheduling.
Time measured in cycles from machine start.
Force compile of block.
Target register allocation enable.
Obsolete attribute that was used to keep information about the current memory transaction if is_stalling is set.
(asn*) is a list of address space numbers corresponding to entries in the DTB.
Current address space number of the DTB.
(pte*) is a list of page table entries in the DTB.
No documentation available.
(tag*) is a list of complete 64-bit tag entries in the DTB.
TRUE if the processor is enabled. If FALSE, it will see time (cycles) pass but not execute steps.
((object, description, time)*). All events in queue with a human-readable description. The attribute is indexed by queue (Sim_Queue_Step/Time).
The floating-point control register.
(f0 ... f31) floating-point registers.
Processor clock frequency in MHz.
Instruction fetch line size for this processor.
Instruction fetch mode
This flag signals whether a sequence of instructions where executed with or without interruption (and is used by RS and RC instructions).
Pending interrupt requests.
When set to 1, the VA register is locked against further updates until read by software.
(ipr0 ... iprN) internal processor registers.
(r0 ... r31) integer registers.
TRUE if the processor is currently stalling by request of a timing-model.
(asn*) is a list of address space numbers corresponding to entries in the ITB.
Current address space number of the ITB.
(pte*) is a list of page table entries in the ITB.
(tag*) is a list of tag entries in the ITB.
(tag*) is a list of complete 64-bit tag entries in the ITB.
Lock flag, used by LDx_L (load-locked) and STx_C (store-conditional) instructions.
Lock granularity of atomic instructions
Address spaced locked by previous LDx_L (load-locked) instruction.
The virtual address associated with LDx_L (load-locked) and STx_C (store-conditional) instructions.
When non-zero, the internal load/store queue is enabled. Only applicable if ooo-mode is "micro-architecture"
(internal) Set debug file for MAI
Base 2 logarithm of memory profiling granularity.
The minimum size (in bytes) of a cache line that can be represented by Simics (when connecting a cache memhier).
Current privilege mode (kernel, executive, supervisor, or user) represented by integers 0 to 3 respectively.
((name, user-value, supervisor-value), ...) List of per-mode counters.
"in-order" or "micro-architecture".
Set to 1 when the processor executes in PAL mode.
Current program counter (PC).
Physical memory space. Must implement both the memory-space and the breakpoint interface.
Simics internal processor number for this CPU. Each processor must have a unique processor number. This attribute can only be set as part of an initial configuration.
(pt0 ... pt7) is a list of PALshadow registers, used as an overlay of the integer register file when operating in PALmode.
The number of cycles the processor will stall
If is_stalling is set, this contains information about the current memory operation.
"constant" indicates a constant finite step/cycle factor; "infinite" means that steps are run without advancing time.
((object, value, slot, step)*). Pending step queue events. object must implement the event_poster interface.
(q, p, r) where q/p is the step per cycle rate, p is a power of 2 and r indicates how much of a cycle that the current step has consumed.
Number steps executed since machine start.
((object, value, slot, cycle)*). Pending time queue events. object must implement the event_poster interface.
Force allocation of memory.
Turbo engine debug level.
Allocate all code space in the current block.
Start of heap.
Max number of blocks.
Max translation unit size.
When set to one, print stats.
Direct stack pointer enable.
Direct DSTC lookup enable.
Off page chaining enable.