(phys-bits, virt-bits) Number of bits in physical and virtual addresses.
A 1-bit field indicating the whether the alternative reset vector (at 0xffff0000-0xffff001c) should be used instead of the vector at 0x00000000-0x0000001c.
((address profiler, view)*) Address profiler views selected for this processor. Affects only the display of profiling information, and has nothing to do with collecting it.
This attribute should contain a list of lists: one list for each address profiler view you want to select (in the order they are to appear), each containing first the address profiler object, then the index of the desired view.
Implemented architecture (arm)
This attribute is TRUE if the processor uses big-endian byte order and FALSE if it uses little-endian.
True if this processor supports branch profiling in -stall mode, false otherwise.
A list of objects (or None) representing coprocessors 0 to 14. (Coprocessor 15 (SCC) is implemented internally by the ARM CPU.) Each coprocessor should implement arm_coprocessor_interface.
The current program status register of each mode. The order of the modes is usr, svc, abt, und, irq, fiq.
The group that this processor belongs to. A cpu group is a collection if cpus that may share memory and/or send interrupts between them. The group must implement the "cpu_group"interface.
Current context object.
Modeling parameter related to processor scheduling.
Time measured in cycles from machine start.
Force compile of block.
Target register allocation enable.
Obsolete attribute that was used to keep information about the current memory transaction if is_stalling is set.
Domain access control
TRUE if the processor is enabled. If FALSE, it will see time (cycles) pass but not execute steps.
((object, description, time)*). All events in queue with a human-readable description. The attribute is indexed by queue (Sim_Queue_Step/Time).
Processor clock frequency in MHz.
The general purpose registers of each mode. The order of the modes is usr, svc, abt, und, irq, fiq.
Instruction fetch line size for this processor.
Instruction fetch mode
TRUE if the processor is currently stalling by request of a timing-model.
Lock granularity of atomic instructions
When non-zero, the internal load/store queue is enabled. Only applicable if ooo-mode is "micro-architecture"
(internal) Set debug file for MAI
Base 2 logarithm of memory profiling granularity.
The minimum size (in bytes) of a cache line that can be represented by Simics (when connecting a cache memhier).
((name, user-value, supervisor-value), ...) List of per-mode counters.
"in-order" or "micro-architecture".
If this attribute is non-zero, then we have a pending exception that will be handled before the next instruction. This will only happen for exceptions that are handled after instruction completion (traps).
Physical memory space. Must implement both the memory-space and the breakpoint interface.
Simics internal processor number for this CPU. Each processor must have a unique processor number. This attribute can only be set as part of an initial configuration.
List of defined SPRs.
The saved program status register of each mode. The order of the modes is usr, svc, abt, und, irq, fiq. The user mode saved program status register is always read as 0 and ignores writes.
The number of cycles the processor will stall
If is_stalling is set, this contains information about the current memory operation.
"constant" indicates a constant finite step/cycle factor; "infinite" means that steps are run without advancing time.
((object, value, slot, step)*). Pending step queue events. object must implement the event_poster interface.
(q, p, r) where q/p is the step per cycle rate, p is a power of 2 and r indicates how much of a cycle that the current step has consumed.
Number steps executed since machine start.
((object, value, slot, cycle)*). Pending time queue events. object must implement the event_poster interface.
Translation table base
Force allocation of memory.
Turbo engine debug level.
Allocate all code space in the current block.
Start of heap.
Max number of blocks.
Max translation unit size.
When set to one, print stats.
Direct stack pointer enable.
Direct DSTC lookup enable.
Off page chaining enable.
True if the processor is in wait for interrupt state.