(phys-bits, virt-bits) Number of bits in physical and virtual addresses.
((address profiler, view)*) Address profiler views selected for this processor. Affects only the display of profiling information, and has nothing to do with collecting it.
This attribute should contain a list of lists: one list for each address profiler view you want to select (in the order they are to appear), each containing first the address profiler object, then the index of the desired view.
Implemented architecture (ppc32)
Lists all available timebase modes (except the default 'null' mode)
This attribute is TRUE if the processor uses big-endian byte order and FALSE if it uses little-endian.
True if this processor supports branch profiling in -stall mode, false otherwise.
The group that this processor belongs to. A cpu group is a collection if cpus that may share memory and/or send interrupts between them. The group must implement the "cpu_group"interface and the ppc-broadcast-businterface.
Current context object.
Modeling parameter related to processor scheduling.
Time measured in cycles from machine start.
Data Address Breakpoint Register
Data address register
((du0,dl0), (du1,dl2),...(du3,dl3)) List for accessing all DBATs
Data BAT lower 0
Data BAT upper 0
Data BAT lower 1
Data BAT upper 1
Data BAT lower 2
Data BAT upper 2
Data BAT lower 3
Data BAT upper 3
Force compile of block.
Cache object affected by data cache control instructions.
Target register allocation enable.
Obsolete attribute that was used to keep information about the current memory transaction if is_stalling is set.
DSI source register
(((valid0, lru0, tag0, eapi0, pte0), (valid1, lru1, tag1, eapi1, pte1)), ...) Data TLB
External access register
TRUE if the processor is enabled. If FALSE, it will see time (cycles) pass but not execute steps.
((object, description, time)*). All events in queue with a human-readable description. The attribute is indexed by queue (Sim_Queue_Step/Time).
(f0, f1, ..., f31) Floating-point registers
Floating-point condition register
Processor clock frequency in MHz.
(r0, r1, ..., r31) General purpose registers
Number of steps spent waiting in nap/doze mode.
Hardware implementation register 0
Hardware implementation register 1
Use host floating point hardware when set to non-zero. This mode is currently only available for 32-bit x86 machines with SSE and SSE2. Supported instructions are fabs, fnabs, fneg, fmr, fadd, fadds, fdiv, fdivs, fmul, fmuls, fsub, fubs, fmadd, fmadds, fmsub, fmsubs, fnmadd, fnmadds, fnmsub, and fnmsubs. The remaining instructions are emulated in software.
Known Limitations: Indeterminism: The simulation can be indeterministic when enabling this mode. NaNs: The calculated result contains incorrect NaN when more than one operand contain NaNs. FPSCR: Only a subset of the FPSCR bits are set correctly. Supported bits are OX, UX, ZX, XX, FI, and FPRF. FX and FEX may be correct if they are generated from the supported bits. Some FPSCR bit can be incorrect for multiply-add/sub instructions.
Instruction Address Breakpoint Register
((iu0,il0), (iu1,il2),...(iu3,il3)) List for accessing all IBATs
Instruction BAT lower 0
Instruction BAT upper 0
Instruction BAT lower 1
Instruction BAT upper 1
Instruction BAT lower 2
Instruction BAT upper 2
Instruction BAT lower 3
Instruction BAT upper 3
Cache object affected by instruction cache control instructions.
Instruction Cache Throttling Control Register
Enable imprecise floating point exceptions when MSR[FE0 FE1] is set to imprecise non-recoverable exceptions.
Non-zero if CPU is in nap/doze mode.
Instruction fetch line size for this processor.
Instruction fetch mode
TRUE if the processor is currently stalling by request of a timing-model.
(((valid0, lru0, tag0, eapi0, pte0), (valid1, lru1, tag1, eapi1, pte1)), ...) Instruction TLB
L2 Control Register
Lock granularity of atomic instructions
When non-zero, the internal load/store queue is enabled. Only applicable if ooo-mode is "micro-architecture"
(internal) Set debug file for MAI
Base 2 logarithm of memory profiling granularity.
The minimum size (in bytes) of a cache line that can be represented by Simics (when connecting a cache memhier).
Monitor Control 0
Monitor Control 1
((name, user-value, supervisor-value), ...) List of per-mode counters.
Machine state register
(bit0name, bit1name... bit32/64name) of the names for each MSR bit defined on this PowerPC processor. Bits not defined are names with an empty string
"in-order" or "micro-architecture".
List of pending exceptions
Name of an interrupt just about to be taken handled
Physical memory space. Must implement both the memory-space and the breakpoint interface.
Performance Counter 1
Performance Counter 2
Performance Counter 3
Performance Counter 4
Simics internal processor number for this CPU. Each processor must have a unique processor number. This attribute can only be set as part of an initial configuration.
Atomic reservation address
Atomic reservation block size
Storage Description Register
Sampled Instruction Address
List of defined SPRs.
Provided for OS use
Provided for OS use
Provided for OS use
Provided for OS use
(sr0, sr1,.., sr15) Segment registers
Machine save/restore register 0
Machine save/restore register 1
The number of cycles the processor will stall
If is_stalling is set, this contains information about the current memory operation.
If set, memory mapped with W=1 will be cached in the STC, making access faster but slowing access for instructions which would trap when W=1. This is for improving simulator performance and should have no other effect.
"constant" indicates a constant finite step/cycle factor; "infinite" means that steps are run without advancing time.
((object, value, slot, step)*). Pending step queue events. object must implement the event_poster interface.
(q, p, r) where q/p is the step per cycle rate, p is a power of 2 and r indicates how much of a cycle that the current step has consumed.
Number steps executed since machine start.
Timebase lower register
Timebase upper register
Temperature of the processor (C)
Thermal Assist Unit Register 1
Thermal Assist Unit Register 2
Thermal Assist Unit Register 3
((object, value, slot, cycle)*). Pending time queue events. object must implement the event_poster interface.
Frequency (in MHz) for time base update
By default, the timebase is connected to the simulated cycles of a processor. Since Simics schedules processors (including hardware threads) in a round-robin fashion, where each processor gets to execute a large amount of instructions, this can cause problems. One example would be when one processor writes the value of timebase to memory at the end of it's quantum, and another processors compares this to the timebase at the beginning of the quantum; time will appear to have moved backwards. Therefore, there are additional timebase modes available that tries to work around these problems. Note that these modes may cause timing irregularies, depending on what software is running on the simulated machine.
The available modes are:
stall - a processor will be stalled til the end of it's quantum whenever it reads the timebase.
quantum-locked - timebase will only change on quantum boundaries.
fast-forward - timebase is fast forwarded when needed and then stopped until time (simulated cycles) has caught up with it.
Unless you know what you are doing, make sure the timebase mode on all processors (of the same class) are the same.
Values of timer registers at quantum start. Used by quantum-locked timebase mode.
If 0, time base/decrementer stand still (internal use only)
Force allocation of memory.
Turbo engine debug level.
Allocate all code space in the current block.
Start of heap.
Max number of blocks.
Max translation unit size.
When set to one, print stats.
Direct stack pointer enable.
Direct DSTC lookup enable.
Off page chaining enable.
Fixed-point exception register
|print-dtlb||print data tlb contents|
|print-itlb||print instruction tlb contents|
|temperature||set or query the temperature of the processor|