(phys-bits, virt-bits) Number of bits in physical and virtual addresses.
((address profiler, view)*) Address profiler views selected for this processor. Affects only the display of profiling information, and has nothing to do with collecting it.
This attribute should contain a list of lists: one list for each address profiler view you want to select (in the order they are to appear), each containing first the address profiler object, then the index of the desired view.
Implemented architecture (sparc-v9)
List of all ASI names
If set to TRUE, Simics will speculate on the value of the CWP register by inspecting save, restore, and return instructions in MAI mode.
This attribute is TRUE if the processor uses big-endian byte order and FALSE if it uses little-endian.
True if this processor supports branch profiling in -stall mode, false otherwise.
Break the simulation if a processor enters error_state
Number of committed instructions for an out of order target.Same as step count for an in-order Simics.
List of all control registers. The attribute supports both integer and string indexed.
The group that this processor belongs to. A cpu group is a collection if cpus that may share memory and/or send interrupts between them. The group must implement the "cpu_group"interface and the sparc-irq-businterface.
Current context object.
Number of the current set of global registers.
Modeling parameter related to processor scheduling.
Time measured in cycles from machine start.
Force compile of block.
Target register allocation enable.
Obsolete attribute that was used to keep information about the current memory transaction if is_stalling is set.
TRUE if the processor is enabled. If FALSE, it will see time (cycles) pass but not execute steps.
External Power Down. Set to 1 when the processor has executed the 'shutdown' instruction.
((object, description, time)*). All events in queue with a human-readable description. The attribute is indexed by queue (Sim_Queue_Step/Time).
The value if this attribute is used as a second interrupt enable flag for the processor. For interrupts to be enabled, the pstate.ie must be 1 and extra_irq_enable must be set to .TRUE. The default value is TRUE.
List of all floating point registers.
Processor clock frequency in MHz.
List of all global registers.
Names of the four sets with global registers.
If TRUE, the upper 32 bits of PC will not be cleared (even if pstate.am is 1) on register writes caused by 'call' 'jmpl', 'rdpc' and traps.
Instruction breakpoint register
Instruction fetch line size for this processor.
Instruction fetch mode
Interrupt queue pointers.
TRUE if the processor is currently stalling by request of a timing-model.
Lock granularity of atomic instructions
When non-zero, the internal load/store queue is enabled. Only applicable if ooo-mode is "micro-architecture"
(internal) Set debug file for MAI
The number of trap levels.
Base 2 logarithm of memory profiling granularity.
The minimum size (in bytes) of a cache line that can be represented by Simics (when connecting a cache memhier).
The associated MMU object, implementing the 'mmu' interface.
((name, user-value, supervisor-value), ...) List of per-mode counters.
If set, unprivileged instruction fetches are not allowed from nucleus ASI.
Number of register windows.
"in-order" or "micro-architecture".
The other strands of the CPU core.
The exception number of any pending exception.
Set to 0x60 (Interrupt_Vector) if an external interrupt is pending. 1 - 15 for soft interrupts.
The exception number of any pending asynchronous trap.
I/O space. Must implement both the memory-space and the breakpoint interface.
Physical memory space. Must implement both the memory-space and the breakpoint interface.
Simics internal processor number for this CPU. Each processor must have a unique processor number. This attribute can only be set as part of an initial configuration.
Register pstate bit mask.
Set to 1 if the CPU should generate lddf/stdf specific align traps for QUAD_LDD/BLK_INIT ASIs.
Pending interrupt queue traps.
The number of instruction currently in the reorder buffer. Only applicable if the target supports out of order execution.
The size of the reorder buffer. Only applicable if the target supports out of order execution.
The RED_state trap vector base address
Simicsfs object used to access the host file-system. If set to non NIL, ASR 31 is used by the simicsfs driver to access the simicsfs device.
The number of cycles the processor will stall
If is_stalling is set, this contains information about the current memory operation.
"constant" indicates a constant finite step/cycle factor; "infinite" means that steps are run without advancing time.
((object, value, slot, step)*). Pending step queue events. object must implement the event_poster interface.
(q, p, r) where q/p is the step per cycle rate, p is a power of 2 and r indicates how much of a cycle that the current step has consumed.
Number steps executed since machine start.
The id number of this strand.
((object, value, slot, cycle)*). Pending time queue events. object must implement the event_poster interface.
List of the time in cycles when a trap has occurred for each trap-level.
Force allocation of memory.
Turbo engine debug level.
Allocate all code space in the current block.
Start of heap.
Max number of blocks.
Max translation unit size.
When set to one, print stats.
Direct stack pointer enable.
Direct DSTC lookup enable.
Off page chaining enable.
The number of bits in the virtual address space. This attribute is used to determine the size of the VA hole. Note that the MMU has it's own handling of the VA hole. The same value will be used for all processors of this class in the system.
List of all window registers.