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6   Limitations

Our model of the CPC700 and the PCI interrupt routing have some problems disallowing any PCI card to be connected at any port.

The linux support for the PM/PPC is not part of the standard linux kernel but have to be provided by Artesyn. This makes it more difficult to compile a kernel for the Simics model.

The subchapter below contains the limitations that exist on the relevant PowerPC processors that can be used with PM/PPC. The SPRs listed do currently have no associated side-effect when either the register is read or written. In many cases this is not a problem even when code do use these registers.

The unimplemented instructions will cause Simics to break execution if the are ever executed.

The instructions implemented as no-operation (NOPs) will just execute without any side-effects at all.

6.1   PowerPC 603e limitations

6.1.1   Unsupported SPRs

None

6.1.2   Miscellaneous Processor Core Limitations


PMC: Performance Monitor Counters (PMC) are not supported.
Little endian mode setting in MSR[LE] is not implemented.
Floating-point estimate instructions are not bit exact.

6.1.3   Unimplemented Instructions

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6.2   PowerPC 750 limitations

6.2.1   Unsupported SPRs

SPR nameNumberDescription
MMCR0952Monitor Control 0
MMCR1956Monitor Control 1
PMC1953Performance Counter 1
PMC2954Performance Counter 2
PMC3957Performance Counter 3
PMC4958Performance Counter 4
SIAR955Sampled Instruction Address

6.2.2   Miscellaneous Processor Core Limitations


PMC: Performance Monitor Counters (PMC) are not supported.
Little endian mode setting in MSR[LE] is not implemented.
Setting ICTC[E] have no impact on instruction fetch cycles.
Floating-point estimate instructions are not bit exact.

6.2.3   Unimplemented Instructions

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6.3   PowerPC 750fx limitations

6.3.1   Unsupported SPRs

SPR nameNumberDescription
HID21016Hardware implementation register 2
MMCR0952Monitor Control 0
MMCR1956Monitor Control 1
PMC1953Performance Counter 1
PMC2954Performance Counter 2
PMC3957Performance Counter 3
PMC4958Performance Counter 4
SIAR955Sampled Instruction Address

6.3.2   Miscellaneous Processor Core Limitations


PMC: Performance Monitor Counters (PMC) are not supported.
Little endian mode setting in MSR[LE] is not implemented.
Setting ICTC[E] have no impact on instruction fetch cycles.
Floating-point estimate instructions are not bit exact.

6.3.3   Unimplemented Instructions

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6.4   PowerPC 750gx limitations

6.4.1   Unsupported SPRs

SPR nameNumberDescription
HID21016Hardware implementation register 2
MMCR0952Monitor Control 0
MMCR1956Monitor Control 1
PMC1953Performance Counter 1
PMC2954Performance Counter 2
PMC3957Performance Counter 3
PMC4958Performance Counter 4
SIAR955Sampled Instruction Address

6.4.2   Miscellaneous Processor Core Limitations


PMC: Performance Monitor Counters (PMC) are not supported.
Little endian mode setting in MSR[LE] is not implemented.
Setting ICTC[E] have no impact on instruction fetch cycles.
Floating-point estimate instructions are not bit exact.

6.4.3   Unimplemented Instructions

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6.5   PowerPC 755 limitations

6.5.1   Unsupported SPRs

SPR nameNumberDescription
L2PM1016L2 Private Memory Control Register
MMCR0952Monitor Control 0
MMCR1956Monitor Control 1
PMC1953Performance Counter 1
PMC2954Performance Counter 2
PMC3957Performance Counter 3
PMC4958Performance Counter 4
SIAR955Sampled Instruction Address

6.5.2   Miscellaneous Processor Core Limitations


PMC: Performance Monitor Counters (PMC) are not supported.
Little endian mode setting in MSR[LE] is not implemented.
Setting ICTC[E] have no impact on instruction fetch cycles.
Floating-point estimate instructions are not bit exact.

6.5.3   Unimplemented Instructions

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6.6   PowerPC 7400 limitations

6.6.1   Unsupported SPRs

SPR nameNumberDescription
MMCR0952Monitor Control 0
MMCR1956Monitor Control 1
MMCR2944Monitor Control 2
PMC1953Performance Counter 1
PMC2954Performance Counter 2
PMC3957Performance Counter 3
PMC4958Performance Counter 4
SIAR955Sampled Instruction Address

6.6.2   Miscellaneous Processor Core Limitations


PMC: Performance Monitor Counters (PMC) are not supported.
Little endian mode setting in MSR[LE] is not implemented.
Setting ICTC[E] have no impact on instruction fetch cycles.
Floating-point estimate instructions are not bit exact.

6.6.3   Unimplemented Instructions

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6.6.4   Instructions Implemented as NOPs

dss[all]

6.7   PowerPC 7447 limitations

6.7.1   Unsupported SPRs

SPR nameNumberDescription
ICTRL1011Instruction cache/interrupt control register
LDSTCR1016Load/Store control register
MMCR0952Monitor Control 0
MMCR1956Monitor Control 1
MMCR2944Monitor Control 2
MSSSR01015Memory subsystem status register
PMC1953Performance Counter 1
PMC2954Performance Counter 2
PMC3957Performance Counter 3
PMC4958Performance Counter 4
PMC5945Performance Counter 5
PMC6946Performance Counter 6
SIAR955Sampled Instruction Address

6.7.2   Miscellaneous Processor Core Limitations


MMU: 36 bit physical address HID0[XAEN] support is not implemented.
PMC: Performance Monitor Counters (PMC) are not supported.
Little endian mode setting in MSR[LE] is not implemented.
Setting ICTC[E] have no impact on instruction fetch cycles.
Floating-point estimate instructions are not bit exact.

6.7.3   Unimplemented Instructions

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6.7.4   Instructions Implemented as NOPs

dss[all]

6.8   PowerPC 7450 limitations

6.8.1   Unsupported SPRs

SPR nameNumberDescription
ICTRL1011Instruction cache/interrupt control register
L3PM983L3 private memory register
LDSTCR1016Load/Store control register
MMCR0952Monitor Control 0
MMCR1956Monitor Control 1
MMCR2944Monitor Control 2
MSSSR01015Memory subsystem status register
PMC1953Performance Counter 1
PMC2954Performance Counter 2
PMC3957Performance Counter 3
PMC4958Performance Counter 4
PMC5945Performance Counter 5
PMC6946Performance Counter 6
SIAR955Sampled Instruction Address

6.8.2   Miscellaneous Processor Core Limitations


MMU: 36 bit physical address HID0[XAEN] support is not implemented.
PMC: Performance Monitor Counters (PMC) are not supported.
Little endian mode setting in MSR[LE] is not implemented.
Setting ICTC[E] have no impact on instruction fetch cycles.
Floating-point estimate instructions are not bit exact.

6.8.3   Unimplemented Instructions

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6.8.4   Instructions Implemented as NOPs

dss[all]

6.9   PowerPC 7457 limitations

6.9.1   Unsupported SPRs

SPR nameNumberDescription
ICTRL1011Instruction cache/interrupt control register
L3ITCR0984L3 cache input timing control register 0
L3ITCR11001L3 cache input timing control register 1
L3ITCR21002L3 cache input timing control register 2
L3ITCR31003L3 cache input timing control register 3
L3OHCR1000L3 cache output hold control register
L3PM983L3 private memory register
LDSTCR1016Load/Store control register
MMCR0952Monitor Control 0
MMCR1956Monitor Control 1
MMCR2944Monitor Control 2
MSSSR01015Memory subsystem status register
PMC1953Performance Counter 1
PMC2954Performance Counter 2
PMC3957Performance Counter 3
PMC4958Performance Counter 4
PMC5945Performance Counter 5
PMC6946Performance Counter 6
SIAR955Sampled Instruction Address

6.9.2   Miscellaneous Processor Core Limitations


MMU: 36 bit physical address HID0[XAEN] support is not implemented.
PMC: Performance Monitor Counters (PMC) are not supported.
Little endian mode setting in MSR[LE] is not implemented.
Setting ICTC[E] have no impact on instruction fetch cycles.
Floating-point estimate instructions are not bit exact.

6.9.3   Unimplemented Instructions

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6.9.4   Instructions Implemented as NOPs

dss[all]

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