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6   Limitations

6.1   PPC603e Limitations

This chapter contains the limitations that exist on the PowerPC 603e processor core. The SPRs listed do currently have no associated side-effect when either the register is read or written. In many cases this is not a problem even when code do use these registers.

The instructions implemented as no-operation (NOPs) will just execute without any side-effects at all.

6.1.1   Unsupported SPRs

None

6.1.2   Miscellaneous Processor Core Limitations


PMC: Performance Monitor Counters (PMC) are not supported.
Little endian mode setting in MSR[LE] is not implemented.
Floating-point estimate instructions are not bit exact.

6.1.3   Unimplemented Instructions

eciwx
ecowx

6.2   PPC440GP Limitations

This chapter contains the limitations that exist on the PowerPC 440GP processor core. The SPRs listed do currently have no associated side-effect when either the register is read or written. In many cases this is not a problem even when code do use these registers.

The instructions implemented as no-operation (NOPs) will just execute without any side-effects at all.

6.2.1   Unsupported SPRs

SPR nameNumberDescription
CCR0947Core Configuration register 0
DBCR2310Debug Control register 2
DBDR1011Debug Data Register
DCDBTRH925Data Cache Debug Tag Register High
DCDBTRL924Data Cache Debug Tag Register Low
DNV0912Data cache normal victim 0
DNV1913Data cache normal victim 1
DNV2914Data cache normal victim 2
DNV3915Data cache normal victim 3
DTV0916Data cache transient victim 0
DTV1917Data cache transient victim 1
DTV2918Data cache transient victim 2
DTV3919Data cache transient victim 3
DVC1318Data Value Compare 1
DVC2319Data Value Compare 2
DVLIM920Data cache victim limit
IAC3314Instruction Address Compare 3
IAC4315Instruction Address Compare 4
ICDBDR979Instruction Cache Debug Data reg
ICDBTRH927Instruction Cache Debug Tag Register High
ICDBTRL926Instruction Cache Debug Tag Register Low
INV0880Instruction cache normal victim 0
INV1881Instruction cache normal victim 1
INV2882Instruction cache normal victim 2
INV3883Instruction cache normal victim 3
ITV0884Instruction cache transient victim 0
ITV1885Instruction cache transient victim 1
ITV2886Instruction cache transient victim 2
ITV3887Instruction cache transient victim 3
IVLIM921Instruction cache victim limit
PIR286Processor ID
RSTCFG923Reset configuration
DBCR1309Debug Control register 1

6.2.2   Miscellaneous Processor Core Limitations


PMC: Performance Monitor Counters (PMC) are not supported.

6.2.3   Unimplemented Instructions

dcread
icread
macchw
macchws
macchwsu
macchwu
machhw
machhws
machhwsu
machhwu
maclhw
maclhws
maclhwsu
maclhwu
mulchw
mulchwu
mulhhw
mulhhwu
nmacchhw
nmacchhws
nmacchw
nmacchws
nmaclhw
nmaclhws

6.2.4   Instructions Implemented as NOPs

dccci
icbt
iccci

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