This chapter contains the limitations that exist on the PowerPC 970fx
The SPRs listed do currently have no associated side-effect when
either the register is read or written. In many cases this is not
a problem even when code do use these registers.
The instructions implemented as no-operation (NOPs) will just
execute without any side-effects at all.
6.1 PowerPC 970fx limitations
6.1.1 Unsupported SPRs
|ACCR||29||Address Compare Control Register|
|MMCR0||795||Performance Monitor Control Register 0|
|MMCR1||798||Performance Monitor Control Register 1|
|MMCRA||786||Performance Monitor Control Register 2|
6.1.2 Miscellaneous Processor Core Limitations
PMC: Performance Monitor Counters (PMC) are not supported.
Floating-point estimate instructions are not bit exact.
6.1.3 Unimplemented Instructions
6.1.4 Instructions Implemented as NOPs