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20.2   Configuration Space

The PCI configuration accesses are implemented with a generic Simics memory-space object. The space is populated by the pci-bus object based on the list provided by the pci_devices attribute. It does not need to be configured manually.

Figure 6. PCI Type 1 Configuration Address in Simics

The configuration space in Simics uses the Type 1 addressing layout (see figure 6), but with the lower bits used for byte addressing. No IDSEL signals are used. This is done to simplify the implementation, and does not impose any restriction of the PCI model.

In the previous example, the configuration space was configured with two devices as follow:

base               object               fn offs               length
0x0000000000000000 pci0                 255 0x0                0x100
0x0000000000001800 dec0                 255 0x0                0x100

The addresses are computed as explained by figure 6, which gives an address of 0x0 for pci0 (bus 0, device or slot 0, function 0) and an address of 0x1800 for dec0 (bus 0, device or slot 3, function 0).

In many systems, typically 32-bit ones, the configuration space is not visible in the global memory-space of the processor. Instead the bridge has a register pair that is used to access the configuration space: one register for the address and one for data.

PCI-to-PCI bridges will automatically add mappings to the configuration space of the primary bus for all subordinate buses. This is done at run-time, since both the secondary and subordinate bus is configured by the simulated software.

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