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16   Memory Transactions

Both CPUs and devices can initiate memory transactions in Simics. For a CPU, the requested virtual address is first translated by the MMU, and an access is performed using the physical address obtained. Device transactions usually skip the translation phase, but are otherwise handled in the same way.

In order to know what a given physical address corresponds to, Simics uses a concept called memory-space. A memory-space maps a physical address to an object that can accept a memory transaction, like RAM, a flash-memory or a device. An access performed in a memory-space is automatically propagated to the right target (device or memory).

Memory-spaces can also contain other memory-spaces as targets which will in-turn map the physical address to a specific object, thus creating a hierarchical organization of memory-spaces. This is often used to separate different types of mapping, or to implement architecture specific differences.

For example, the memory mappings of a one-processor Serengeti system (in this case sarek-common.simics) at boot time is based on two memory-spaces: phys_io0 (the I/O space) and phys_mem0 (the memory space). They contain the following mappings:

base               object               fn offs               length
0x0000000000000000 memory                0 0x0                0x10000000
0x000007fff07ffff0 hfs                   0 0x0                0x10

base               object               fn offs               length
0x0000040000400000 mmu0                  0 0x0                0x48
0x000004000c000000 schizo24              0 0x0                0x800000
0x000004000c800000 schizo25              0 0x0                0x800000
0x000007fff0000000 cpuprom               0 0x0                0xbd3b0
0x000007fff0102000 fpost_code            0 0x0                0x2000
0x000007fff0104000 fpost_data            0 0x0                0x2000
0x000007fff0800060 empty0                0 0x60               0x10
0x000007fff091e000 empty1                0 0x0                0x120

Simics allows you to observe and sometimes modify the behavior of the transactions that go through the memory system. The rest of this chapter will present the basic concepts behind Simics's memory system and how to interact with it.

16.1   Observing Memory Transactions

16.2   Stalling Memory Transactions

16.3   Observing Instruction Fetches

16.4   Simulator Translation Cache (STC)

16.5   Summary of Simics Memory System

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