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16.2   Stalling Memory Transactions

When an object attached to the timing-model interface receives a memory-transaction, it is allowed to modify the timing of the transaction by returning a stall time (as a number of processor cycles). Upon receiving a non-zero stall time, Simics will block the transaction for that number of processor cycles before executing it.

This behavior is a key to modeling caches and memory hierarchies in Simics, particularly in multi-processor simulations. A complete description of cache simulation in Simics is available in chapter 18. The Simics Programming Guide explains how to make your own timing-model object to observe and stall memory transactions, and provides more information about the different types of stalling available.

To be able to stall transactions, the simulation must be started with the -stall flag. This will tell Simics to set up the processors so that stalling is allowed. It is otherwise disabled for performance reasons.

Stalling a transaction is not always possible, depending on the processor model you are using in the simulation:

Note: As mentioned above, a transaction may go through several memory-spaces in hierarchical order before being executed. Each of these memory-spaces may have a timing-model connected to them. However, if the transaction is stalled by one timing model, the other timing models may see the transaction being reissued before it is executed.

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