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16.5   Summary of Simics Memory System

To summarize the different concepts introduced in this chapter, here is a description of the path followed by a processor transaction through Simics memory system.

Figure 4. Transaction Path through Simics Memory System

  1. The CPU executes a load instruction.
  2. A memory transaction is created.
  3. If the address is in the STC, the data is read and returned to the CPU using the cached information.
  4. If the address is not in the STC, the transaction is passed along to the CPU memory-space.
  5. If a timing-model is connected to the memory-space, it receives the transaction.

    1. If the timing model returns a non-zero stalling time, the processor is stalled and the transaction will be reissued when the stall time is finished.
    2. If the timing model return a zero stall time, the memory-space is free to execute the transaction.
  6. The memory-space determines the target object (in this example, a RAM object).
  7. The RAM object receives the transactions and executes it.
  8. If possible, the transaction is inserted in the STC.
  9. If a snoop-memory is connected to the memory-space, it receives the transaction.
  10. The transaction is returned to the CPU with the correct data.

Store operations works in the same way, but no data is returned to the CPU.

Note: Simics's memory system is more complex than what is presented here, but from the point of view of a user timing-model or snoop-memory, this diagram explains correctly at which point the main different events happen.

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