Previous - Up - Next

18.8   Speeding up g-cache simulation

By default, g-cache will try to use the STCs to minimize the number of transactions that it has to handle while still providing correct statistics and behavior.

Simulating a data cache
If you are only interested in data accesses, g-cache can use the Data STC and still provide correct statistics. To allow g-cache to use the Data STC, you should set the penalty_read and penalty_write to 0 (so that cache hits do not take any penalty). g-cache will then allow cache hit transactions to be saved in the Data STC and use its internal counters to report a correct number of total transactions, and thus correct ratios.

Note that when using the Data STC counters, g-cache can not determine to which memory space the accesses reported by the DSTC belong to, so you need to connect g-cache to all the memory spaces to which the processor is talking. In practice, the processor often talks to one main memory space and nothing special needs to be done. Sun's UltraSPARC machines, however, have separate physical memory and physical I/O spaces. The cache should then be connected to both of them. Another way of solving this problem is to connect a small module that will prevent accesses to other memory spaces from being cached in the Data STC.

Simulating an instruction cache
When simulating an instruction cache, g-cache is able to use the Instruction STC to speed up the simulation and report the number of instruction misses, but it won't report the correct number of total transactions. If you wish to have a correct total amount of instruction fetches, you need to disable ISTC usage at the command-line with the istc-disable command.

You can always prevent g-cache from using the STCs if you encounter one of the limitations mentioned later in this chapter, by setting the config_block_STC attribute of the cache to 1.

Previous - Up - Next