This is a resolved version of the
std_ulogic, a signal or variable of this type can take on the following values:
'U': uninitialized. This signal hasn't been set yet.
'X': unknown. Impossible to determine this value/result.
'0': logic 0
'1': logic 1
'Z': High Impedance
'W': Weak signal, can't tell if it should be 0 or 1.
'L': Weak signal that should probably go to 0
'H': Weak signal that should probably go to 1
'-': Don't care.
The basic VHDL logic operations are defined on this type:
not. They can be used like the built-in operations on the bits.
signal s1, s2 : std_logic; ... variable v1, v2 : std_logic; ... s1 <= '0'; v1 := '1'; s2 <= 'X'; wait for 10 ns; s2 <= s1 and v1; -- '0' v2 := s1 or v1; -- '1'