No attempt has been made here to be definitive or exhaustive. If you want real answers, read the source code. Links to the code or instructions on how to get it are provided for each section. The source is fairly readable to someone who knows some VHDL.
This page was created in response to a glaring lack of documentation about these libraries on the web. Hopefully they can be used by both SFU students and others who are learning VHDL or want a light reference to the
These pages do not attempt to teach VHDL. The scope is restricted to the
std_logic libraries and their extensions.
If you notice errors on these pages or feel that some important material has been left out, feel free to email Greg.
These pages are published under the GNU Free Documentation License, so you can copy and republish them as allowed by that license.
If you would like a copy of all of the pages for mirroring or your own use, you can download them as either a gzipped TAR or a ZIP file.