## Correlation Bounds and #SAT Algorithms for Small Linear-Size Circuits

#### Ruiwen Chen and Valentine Kabanets

### Abstract

We revisit the gate elimination method, generalize it to prove correlation bounds of boolean circuits with Parity, and also derive deterministic #SAT algorithms for small linear-size circuits. In particular, we prove that, for boolean circuits of size $3n - n^{0.51}$, the correlation with Parity is at most $2^{-n^{\Omega(1)}}$, and there is a #SAT algorithm running in time $2^{n-n^{\Omega(1)}}$; for circuit size $2.99n$, the correlation with Parity is at most $2^{-{\Omega(n)}}$, and there is a #SAT algorithm running in time $2^{n-{\Omega(n)}}$. Similar correlation bounds and algorithms are also proved for circuits of size almost $2.5 n$ over the full binary basis $B_2$.

### Versions

- conference version in
*Proceedings of the Twenty-First Annual International Computing and Combinatorics Conference (COCOON'15)*, pages 211-222, 2015. -
preliminary full version in
*Electronic Colloquium on Computational Complexity*ECCC-TR14-184, 2014.