Github clone link

On CSIL you may need the following before you can run the commands

pip3 install --user colorama
pip3 install --user pandas

Github Clone Link

RISC V Pipeline

In this part you will be working through the running of a program on a RISC-V processor. The processor we provide you is similar to the one discussed in class as is shown below. There are five stages IF, ID, EX, MEM, WB.

In the absence of hazards each instruction takes five cycles to run proceeding sequentially through each stage. A new instruction is produced every cycle.

Hazards

# WARNING: Web model link Web-RISCV on lectures page does not precisely follow the conditions listed here so read instructions carefully.

Hazards occur in a pipeline when different pipeline stages need to access share data or resources (e.g., dependent instructions occurring in back-to-back). There are two options to deal with hazards stalling and forwarding. In our pipeline we assume that apart from control dependencies all other dependencies are handled using forwarding.

• Branches are resolved in the execution stage. Instructions following branch in IF and ID stage are flushed.
• Dependencies between the R-type instruction and branches are resolved by forwarding. i.e., No stalls are needed if the R-type instruction is followed by a data-dependent instruction.
• You can assume the memory ops complete in 1 cycle

We now discuss the conditions which lead to stalls.

• Load data stall condition for load-to–use case. Handle instructions where a load and its dependent instruction occur back-to-back. When a data stall occurs the pipeline in the EX stage is filled with a - (a space) in the subsequent cycle i.e. hold the instruction in decode stage for 1 cycle

      exe-stall := ((EX.is_load) && (EX.rd === ID.rs1)  ||
               ((EX.is_load) && (EX.rd === ID.rs2)

• Control Hazard when the next instruction is not PC+4 (exe_nextpc != PC + 4) i.e., the next instruction calculated in the EX stage is not equal to the next instruction in the code listing. Then the instruction fetch needs to be killed for current instructions in the pipeline. This implies setting the IF and ID to “ “ for the subsequent cycle.

if (type == BR_NE) && neq == True
// ==
if (type == BR_EQ) && eq == True
// >=
if (type == BR_GE) && !lt == True
// LT
if (type == BR_LT) && lt == True
// J
if (type == BR_J) || (br_type = jalr)

– Environment Calls - Finally when you have ecall it has to stall in the EX stage until instructions ahead in the MEM and WB stage have completed.

Tasks

We have provided pipeline timing sheets on google. Please copy and create your own sheet. Your goal is to walk through the simulation of the 5-stage processor and fill out the sheet. In each cycle, fill out the pipeline stages. Each cell will contain one of either IF, ID, EX, MEM, WB, - (bubble or stall), or is empty if corresponding instruction is not in pipeline.

An example program has been provided to illustrate. It includes a sheet that is already filled out. The sheet is organized as follows.

The example sheet shows the pipeline execution of the example program.Example Sheet. Select at bottom. Note that instructions listed in the sheet are after the program has been assembled i.e., all the jump targets are absolute addresses and instructions can only use x registers.

The pipeline is post assembly and instruction execution starts at address 0.

Symbols

• In the .s you will see pseudo instructions such as example.s:line 10 la a0,answer. These will be translated to a single auipc instruction (in the pipeline sheet). If you do not know what la does refer to the RISC-V card. It obtains the pointer to variable answer and stores it in a0.
• In the .s you will also find example.s:line 20 lw t0,arg1. These will get translated to a combination of auipc and load instructions.

WARNING: 0x65536 in AUIPC instruction read as decimal 65536 or hex 0x10000 DO NOT FIX IT THOUGH. YOUR TEST WILL NOT PASS

Note that the programs have jump instructions so the order in which instructions run is not necessarily the order in which they are listed in the first column.

Pipeline restarts after a jump target simply flush the entire pipeline and start from a new instruction that is the jump target e.g., jal x1 0x28, when instruction reaches EX stage, subsequent instructions are flushed and execution starts with an IF of the jump target in the next cycle, instruction at 0x28 auipc.. in this case.

Assembly

Here is the assembly listing of the programs:

• .data segment starts at 0x10000000

• .code segment starts at 0x0

• [Example.s]
  • This program simply adds two numbers
• [JTable.s]
  • This program implements a jump table; the choice is 2.
• [Loop1]
  • See .s for C code illustration
• [Loop2]
  • See .s for C code illustration.

Validation

To validate the design you need to export a CSV from the google sheets. This script will verify the pipline stages cycle-by-cycle. It will stop at the first cycle where your entry mismatches with the actual answer and display the incorrect instructions in red.

Common error 1: Please remember that pipeline flushes are indicated by an empty cell, while pipeline bubbles are indicated by - Common error 2: Letter case of pipeline stages. Only upper case is accepted; only IF is valid.

python3 decrypt.pyc -F Example_Pipeline.enc -C Example_Pipeline.csv # Correct simulation
python3 decrypt.pyc -F Example_Pipeline.enc -C Example_Error_Pipeline.csv # Incorrect simulation

Check after every few instructions. The checker will tell you the line upto which you passed and whether instruction is wrong or the stage

# Download google sheet as Loop1.csv Fill and check
python3 decrypt.pyc -F Loop1.enc -C Loop1.csv
# Download google sheet as Loop2.csv
python3 decrypt.pyc -F Loop2.enc -C Loop2.csv
# Download google sheet as JTable.csv
python3 decrypt.pyc -F JTable.enc -C JTable.csv

How to download as csv