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Critical thinking

This is a 400-level course (cross-listed with a graduate course) which implies that students practice a level of critical thinking when reading book chapters, papers and slides. This is an online model on how to practice critical thinking.

The syllabus listed weekly includes lecture slides, short video aids, demos, written problems, and reference to book chapters. Please ensure that you go over all the relevant material.

Syllabus

Keys: Code. Handouts Video.

Week 1 - Superscalar processors, Out-of-order execution, Dependencies

Lecture notes

Book Chapters

  • ARCH: Appendix C.1, C.2 (Read till before Reducing pipeline branch penalties)
  • ARCH: Chapter 3.1 (Read)
  • ARCH: Chapter 3.8 (Skim)
  • J. Smith and G. Sohi, The Microarchitecture of Superscalar Processors, Proc. IEEE, 1995. (Read)

Week 2 - Branch prediction, Precise Interrupts

Lecture notes

Book Chapters

  • ARCH: Appendix C.2 (Start at Reducing pipeline branch penalties)
  • ARCH: Chapter 3.3,3.4, 3.5, 3.6 (Read)
  • ARCH: Chapter 3.7, 3.8 (Skim)
  • (750 Students): A. Seznec, The L-TAGE Branch Predictor, Journal of Instruction Level Parallelism, 2007, https://jilp.org/vol9/v9paper6.pdf (Read)

Week 3 - Issue Logic and Memory Ordering

Lecture notes

Additional Notes

Book Chapters

  • S. Palacharla et al, Complexity-Effective Superscalar Processors, ISCA 1997
  • G.Z. Chrysos and J.S. Emer, Memory Dependence Prediction using Store Sets, ISCA 1998

Week 4 - Memory Hierarchy

Lecture notes

Book Chapters

  • ARCH:2.1, 2.2, 2.3, 2.4 (Read), Appendix B (Skim)

Week 5 - Cache Management

Lecture notes

Book Chapters

  • N. Jouppi, Improving Direct-Mapped Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffer, ISCA 1990 (Read)
  • T.F. Chen and J.L Baer, Effective Hardware-Based Data Prefetching for High-Performance Processors, IEEE Transactions on Computers, 1995 (Skim)
  • O. Mutlu et al., Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors, HPCA 2003 (Skim)
  • M. Shevgoor et al., Efficiently Prefetching Complex Address Patterns, MICRO 2015 (Skim)"
  • M. Qureshi et al., Adaptive Insertion Policies for High-Performance Caching, ISCA 2007 (Read)"
  • A. Jaleel et al., High Performance Cache Replacement Using Re-Reference Interval Prediction (RRIP), ISCA 2010 (Skim)"

Week 6 - Parallel Architectures

Lecture notes

Book Chapters

  • ARCH:5.1,5.2 (Read)
  • Hill and Marty, Amdahl Law in the Multicore Era, IEEE Computer, 2008 (Read)
  • Lawrence Livermore National Lab, Introduction to Parallel Computing, https://hpc.llnl.gov/training/tutorials/introduction-parallel-computing-tutorial (Skim)

Week 7 - Cache Coherence

Lecture notes

Book Chapters

  • ARCH:5.2,5.3,5.4 (Read)
  • D. Lenoski et al., The Directory-based Cache Coherence Protocol for the DASH Multiprocessor, ISCA 1990 (Read)
  • P. Stenstrom, A Survey of Cache Coherence Schemes for Multiprocessors, IEEE Computer, 1990 (Skim)
  • J. Laudon and D. Lenoski, The SGI Origin: A ccNUMA Highly-Scalable Server, ISCA 1997 (Skim)

Week 8 - Technology

Lecture notes

Book Chapters

  • ARCH: Chapter 1.1, 1.4, 1.5 (Read)
  • ARCH: Chapter 1.6 (Skim)
  • S. Gochman et al, The Intel Pentium M Processor Microarchitecture and Performance, Intel Technology Journal 2003 (Skim)

Week 9 - DSA I

Lecture notes

Book Chapters

  • ARCH:Chapter 7

Week 10 - DSA II

Lecture notes

Book Chapters

Week 11 - Memory

Lecture notes

Book Chapters

  • ARCH:5.6,5.7 (Read)
  • S. Adve and K. Gharachorloo, Shared Memory Consistency Models: A Tutorial, Technical Report, 1995
  • B. Jacob, S. Ng, D. Wang, Memory Systems: Cache, DRAM, Disk, Chapter 7(Read), Chapter 8(Skim)

Week 12 - Multithreading

Lecture notes

Book Chapters

  • VLIW ARCH:3.2,3.7,3.12
  • Simultaneous Multithreading ARCH:3.12
  • D. Tullsen et al, Simultaneous Multithreading: Maximizing On-Chip Parallelism, ISCA 1995 (Read)
  • G. Sohi et al, Multiscalar Processors, ISCA 1995 (Read)

Reference Papers